ASIC Design Verification Engineer
$175,000–$215,000 year
Hybrid · Mountain View Santa Clara County, California, United States
Job Summary
ASIC Design Verification Engineer at Waymo — hybrid schedule in Mountain View, CA. You will translate hardware specs into verification plans, develop testbenches and reference models, integrate third-party Verification IP, and define coverage metrics to ensure design readiness. You’ll architect and enhance verification environments, collaborate across teams, and advocate verification best practices. Required skills include UVM/SystemVerilog testbenches with constrained-random generation and functional coverage, SystemVerilog Assertions, Python for automation, and strong debugging across RTL and testbench layers. Preferred experience includes post-silicon bring-up, UPF/formal verification, ML accelerators, NoCs, and PCIe DDR5/Ethernet interfaces, with a focus on scalable verification and automation.
Required Qualifications
- 3+ years of experience building and maintaining complex testbenches using UVM/SystemVerilog
- Proven track record with constrained-random generation, functional coverage, and SVA (SystemVerilog Assertions)
- Deep understanding of complex digital logic and debugging hardware/software interactions
- Proficiency in Python for automation frameworks, data analysis, and regression management
- Excellent verbal and written communication skills, ability to collaborate with cross-functional teams
- Strong analytical skills in root-causing failures across RTL, testbench, and environment layers
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