ASIC Design Verification Engineer, Technical Leader
$183,800–$263,600 year
On-siteSan Jose, California, United States
Job Summary
ASIC Design Verification Engineer, Technical Leader in Cisco’s CHG Silicon One group based in San Jose, CA. Responsible for maintaining and enhancing DV environments, constructing test benches (including scoreboard, agents, sequencers, and monitors) for new blocks, writing test plans, debugging regression failures, and driving verification closure. Ensure complete verification coverage through implementation and review of code and functional coverage, and apply AI-driven approaches to improve design verification quality. Collaborates with verification engineers, designers, hardware, and cross-functional teams to verify the ASIC in simulation, emulation, and bring-up.
Required Qualifications
- Bachelor’s degree with 8+ years or Master’s degree with 6+ years of relevant experience
- Proven experience with SystemVerilog and UVM methodology
- Experience verifying complex blocks, clusters, and/or top-level ASIC/SoC
- Experience building test benches from scratch, hands-on with SystemVerilog constraints, structures, and classes
- Experience with functional coverage and constrained-random DV environments
- Scripting skills: Perl and/or Python
Desired Qualifications
- Strong domain experience in PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU
- Experience with Veloce/HAPS is a plus
- Formal verification (iev/vc formal) knowledge is a plus
- Experience with System Verilog and UVM for ASIC/SoC verification
- Scripting skills in Perl and/or Python
- Knowledge of verification methodologies, test bench development, and regression debugging
- Ability to collaborate with cross-functional teams and bring-up verification on silicon
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