ASIC Design Verification Engineer
On-siteMinneapolis, Minnesota, United States
Job Summary
Develop and maintain UVM-based SystemVerilog verification environments for advanced SOC designs, including building Python-based testbenches and simulation infrastructure. Execute block and system-level verification plans while collaborating with design teams to debug complex functional and integration issues. Drive coverage closure and continuously improve verification quality metrics using constrained random verification techniques. Explore and adopt AI-assisted tools to enhance verification productivity and debugging efficiency. Requires 2+ years of IP or SoC verification experience with proficiency in SystemVerilog and Python.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent
- 2+ years of proven experience in IP or SoC verification
- Hands-on experience with UVM and constrained-random verification
- Strong proficiency in SystemVerilog and Python
- Proven analytical, debugging, and communication skills
- familiar with constrained random verification and functional coverage closure
- self-starter
- excellent analytical and problem solving/debugging skills
- excellent verbal and written communication skills
- ASIC/FPGA design verification experience with UVM methodologies
- Develop and maintain UVM‐based SystemVerilog verification environments
- Build and enhance Python‐based testbenches and simulation infrastructure
- Execute block and/or system‐level verification plans
- Debug complex functional and integration issues in close collaboration with design teams
- Drive coverage closure and continuously improve verification quality metrics
- Excellent problem-solving skills
- Phenomenal teammate with excellent interpersonal communication skills
Desired Qualifications
- Experience with mixed‐signal verification
- Experience with DRAM protocol: DDR/LPDDR/GDDR
- Experience working in fast‐paced, highly collaborative engineering environments
- Interest in applying AI/ML techniques to improve verification flows, automation, or productivity
- opportunities to adopt and influence emerging AI‐based approaches that improve verification productivity, debugging efficiency, and quality
- Explore and adopt AI‐assisted techniques and tools to improve verification productivity and debug efficiency
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