ASIC Design Verification Engineer (all levels)
RemoteSunnyvale, California, United States
Sunnyvale, California, United StatesRemoteFull TimeMedium
Full TimeMedium
Job Summary
Architect and build SoC-level and unit-level UVM verification environments while collaborating with Architecture and Design teams to verify chip features against use scenarios. Construct test plans, develop directed or constrained random vectors to close coverage, and integrate third-party VIPs into test benches. Debug test failures by identifying root causes and maintain daily and weekly regression suites. This role supports the development of a latency-optimized SoC for mission-critical real-time applications, leveraging proven AI accelerator designs to achieve best-in-class performance.
Required Qualifications
- A minimum of 10+years (Principal) / 7+ years (Senior Staff) / 5+ years (Staff) of design verification experience with 1+ years of leader role (for Lead position)
- Must possess prior experience in developing a complete chip-level UVM test bench from scratch (for principal / Lead role)
- Expert in coverage driven System verilog UVM with DPI-C, including UVM runtime phases (for Lead/Principal role)
- Proficient in programming in C/C++, python and/or scripting language
- Prior experience in ASIC design verification
- In-depth knowledge in bus fabrics; NoC, AMBA etc in multi-CPU environment
- BSEE/BSCE required
- Master in Science preferred
Desired Qualifications
- Prior experience in verifying instruction driven designs like CPUs and GPGPUs
- Understanding of chip security, cold/warm boot sequences
- Experiences using SERDES based high speed interfaces, i.e. MIPI, PCIe and USB
- FPGA prototyping experience
- Knowledge in ISO-26262 ASIL compliances
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