ASIC Design Engineer
On-site · Bengaluru, Karnataka, India
Job Summary
ASIC/SoC Design Engineer to join one of the industry leaders in Smart Edge SoCs for network/system control, management security systems, and IIoT. The role involves developing the design and implementation of SoCs, micro-architecture design, RTL coding, synthesis, timing closure, and documentation of RTL blocks; optimizing performance, bandwidth, and power; collaborating with FPGA engineers for early prototyping; supporting test programs, chip validation, and production maturity; and working with firmware, software, DV, FPGA, DFT, and backend teams across the ASIC development lifecycle. Requires 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization, proficiency in Verilog, knowledge of RTL synthesis and timing closure, familiarity with multiple interface protocols (PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART), FPGA emulation experience (HAPS, Veloce), scripting (Python/Perl), and having completed at least one tapeout.
Required Qualifications
- 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization
- Proficient in writing clear, implementable micro-architecture specifications
- Expertise in writing efficient RTL code in Verilog and SoC integration
- Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure
- Experience with interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART
- Experience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce
- Fluency with scripting languages (e.g., Perl, Python)
- Must have gone through at least one tapeout
- Preferred: Silicon bring-up and debug experience
- Experience with Bitbucket/Jenkins and JIRA
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