ASIC Design Engineer
On-site · Taipei, Taiwan, Taiwan
Job Summary
ASIC/SoC Design Engineer for leading Smart Edge SoCs in network/system control, management security, and IIoT. Responsibilities include micro-architecture design, RTL coding, synthesis, timing closure, performance and power optimization, FPGA-assisted prototyping, test program development, chip validation, and collaboration across firmware, software, DV, FPGA, DFT, SoC integration, and backend teams. Requires 8+ years of RTL design experience, Verilog proficiency, ability to write clear architecture specifications, knowledge of multiple interface protocols (PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART), FPGA emulation experience (HAPS/Veloce), scripting in Perl/Python, and at least one tapeout. Preferred: silicon bring-up and debug experience; experience with Bitbucket/JIRA. Based in Taipei, Taiwan.
Required Qualifications
- 8+ years of RTL logic design, verification, synthesis, and timing optimization
- Proficiency in writing clear, implementable micro-architecture specifications
- Expertise in writing efficient RTL code in Verilog and SoC integration
- Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure
- Experience with interface protocols: PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART
- Experience in design bring-up and debug on FPGA-based emulation platforms like HAPS, Veloce
- Fluency with scripting languages (Perl, Python)
- Must have gone through at least one tapeout
- Preferred: Silicon bring-up and debug experience
- Experience with repository management tools (Bitbucket) and bug tracking tools (JIRA)
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