ASIC Clocks Design Engineer - New College Grad 2026
$100,000–$189,750 year
On-site · Austin, Texas, United States or Santa Clara, California, United States
Job Summary
ASIC Clocks Design Engineer to architect clock domains for GPU/CPU, collaborate with front-end design, physical/digital teams, and silicon bring-up; contribute to clocking topologies and RTL clocking information delivery across verification, timing, and DFx teams, with emphasis on power, performance, and area trade-offs and end-to-end ASIC execution; ideal candidates have RTL (Verilog), Python scripting, and cross-team collaboration skills for clocking-related challenges.
Required Qualifications
- Bachelor's degree in Electrical Engineering or equivalent
- Experience in RTL design (Verilog) and verification
- Strong coding skills in Python or scripting languages
- Ability to collaborate with multiple teams (GPU/CPU/SoC, physical design, timing, verification, SW)
- Understanding of logic optimization techniques and PPA trade-offs
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