ASIC Architect
On-site · San Jose, California, United States
Job Summary
The ASIC Architect role involves developing and optimizing compute architectures for AI accelerators, focusing on throughput, latency, and power efficiency. Responsibilities include designing chip architectures for AI/ML workloads, contributing to next-generation silicon design, creating architectural specifications, collaborating with cross-functional teams, and conducting performance optimizations. Candidates are required to have a PhD and at least 5 years of relevant experience, alongside a strong understanding of computer architecture and proficiency in programming languages for modeling.
Required Qualifications
- PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field
- 5+ years of experience in computer architecture, ASIC design, or related fields
- Strong understanding of computer architecture fundamentals including pipelines, memory hierarchies, and interconnects
- Experience with performance modeling and architectural simulation tools
- Hands‐on experience designing and optimizing floating‐point datapaths or arithmetic‐intensive circuits and working with advanced process nodes.
- Proficiency in Rust, C/C++, or Python for modeling and analysis
- Knowledge of modern processor microarchitecture and design tradeoffs
- Strong analytical and problem-solving skills with attention to detail
- Excellent communication skills and ability to work in cross-functional teams
Desired Qualifications
- AI/ML accelerator architectures and dataflow optimization
- RTL design and verification (Verilog/SystemVerilog)
- Cycle-accurate simulation tools (gem5, SystemC, or custom simulators)
- Power and performance analysis methodologies
- ASIC design flow and physical design constraints
- Publishing or presenting at architecture conferences (ISCA, MICRO, HPCA, etc.)
- Hands-on experience with tapeout and silicon bring-up
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