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Astera Labs9 months ago

Analog/Mixed-Signal Engineer - SerDes (PhD Intern 2026)

$114,400–$135,200 year

On-site · Irvine, California, United States

Type
Internship
Level
Entry Level
Education
Masters Degree
Company size
Unknown
Industry
Semiconductors

Job Summary

Intern Analog/Mixed-Signal IC Design Engineer focusing on designing and verifying high-speed mixed-signal circuits (PLL, DLL, ADC/DAC, TX/RX, CDRs) for SerDes connectivity. Develop and verify analog and clocking blocks, use industry-standard tools such as Spectre and MATLAB, and collaborate with global teams. Pursuing Master’s or PhD in EE is preferred. Experience in high-speed analog/digital design, CMOS nodes (20nm or newer), noise/jitter analysis, and familiarity with optical transceivers or RFIC design highly desirable.

Required Qualifications

  • Pursuing a Master’s or PhD degree in Electrical Engineering is preferred
  • Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs
  • Deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
  • Solid fundamentals in transistor-level design, feedback/stability analysis, and noise/jitter analysis
  • Experience with PCB design; familiarity with optical transceivers and RFIC design desirable
  • Proficiency with Python, Matlab, or C; familiarity with Verilog RTL or DSP concepts
  • Strong teamwork, presentation and documentation skills; ability to collaborate across time zones

Desired Qualifications

  • Pursuing a Master’s or PhD degree in Electrical Engineering (EE) is preferred
  • Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs
  • Experience with biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
  • Solid fundamentals in transistor-level design, feedback/stability analysis, and noise/jitter analysis
  • Knowledge of TIA design and drivers for optical applications is highly desirable
  • Familiarity with Verilog RTL or DSP concepts; Python, Matlab, or C programming
  • Experience with PCB design; RFIC design for wireless or wireline systems is desirable
  • Strong teamwork, documentation skills; ability to collaborate across time zones
  • Campus/internship eligibility and ongoing graduate study
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$114k – $135k / yr

Analog/Mixed-Signal Engineer - SerDes (PhD Intern 2026) · Astera Labs

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