Analog Layout engineer
$2,500,000–$2,500,000 year
On-siteBengaluru, Karnataka, India
Job Summary
Conduct toplevel integration and block level analog layouts for ADC/DAC/PLL and high-speed Serdes in 7nm and 5nm nodes. Execute floor planning, matching, EM/IR, and DFM implementation from scratch while managing LVS, density, lower node DRCs, and parasitic reduction. Utilize industry standard EDA tools including Cadence Virtuoso and Mentor Graphics Caliber to run Spice and cosim simulations for AMS blocks. Develop analog checkers and execute regression across operating conditions, leveraging digital verification skills in SystemVerilog and UVM. Prioritize candidates with TSMC/Samsung or Serdes project exposure over Intel-only resumes.
Required Qualifications
- Very good understanding of semiconductor and analog basics
- Good hands-on experience in toplevel integration and block level analog layouts like ADC/DAC/PLL/high speed Serdes, Power Management blocks
- Good Experience with floor planning, matching, EM/IR and DFM issues and other analog layout related concepts and hands on implementation from scratch
- Experience of LVS, Density, lower node DRC's, Parasitic reduction and other lower node challenges
- Good experience in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
- Good problem solving and logical reasoning skills
- Good communication skills
- Analog Mixed signal verification experience
- Understanding CMOS analog design like References, Amplifiers, Comparators, etc.
- Running spice and cosim simulations for analog/AMS blocks like ADCs, PLLs etc.
- Writing analog checker and running regression across operating conditions
- Digital verification skill and strong knowledge on systemverilog and UVM
Desired Qualifications
- N3E or lower node experience
- TSMC/Samsung/serdes projects are preferable to have in resumes
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