AIML enhanced Design/Verification Methodology Engineer
$81,400–$164,400 year
On-siteSunnyvale, California, United States
Job Summary
Architect, build, and maintain UVM-based testbench environments while developing comprehensive verification strategies for complex digital designs using AIML-enhanced methodologies. Create verification plans with clear coverage goals, automate RTL generation from specifications, and perform root cause analysis to drive resolution with design teams. Collaborate closely with system engineering to ensure silicon quality from RTL to tapeout by leveraging both classical and generative-AI methodologies for agent and infrastructure development. This onsite role at Hewlett Packard Enterprise requires deep familiarity with AIML concepts, SystemVerilog, and industry-standard simulation tools to solve intricate design challenges.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent)
- 1 - 5 years of hands-on Design/Verification experience in an ASIC or SoC environment
- Deep familiarity with AIML concepts and workflows — including awareness of agentic workflows, APIs, model selection, etc.
- Strong proficiency in SystemVerilog for verification (classes, constraints, functional coverage, assertions/SVA)
- Solid understanding of digital design fundamentals (RTL, timing, synthesis constraints)
- Experience with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)
- Proven ability to develop and drive verification plans to closure
- Effective communication and collaboration skills in cross-functional team settings
Desired Qualifications
- Master's or Ph.D. in Electrical Engineering or Computer Science
- Academic or professional class projects or coursework in networking, communication protocols (e.g., Ethernet, PCIe, USB, AMBA/AXI, SPI, I2C, UART), or related areas
- Experience verifying high-speed serial interfaces or protocol-level IP blocks
- Familiarity with formal verification tools and techniques (e.g., JasperGold, VC Formal)
- Experience with emulation and FPGA prototyping platforms (e.g., Palladium, Protium, Veloce)
- Knowledge of scripting languages (Python, Perl, TCL) for automation of verification workflows and regression infrastructure
- Experience with power-aware verification (UPF/CPF) or mixed-signal verification
- Contributions to verification methodology development or published work in the field
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