Advanced Power Integrity & Power Delivery Architect
$237,200–$296,500 year
On-sitePalo Alto, California, United States
Palo Alto, California, United StatesOn-siteFull Time$237,200–$296,500 yearDoctorate Or Professional DegreeEnterprise
Full TimeDoctorate Or Professional DegreeEnterprise
Job Summary
Define and optimize SoC power architecture, establishing target impedance and efficiency targets across the full path from silicon to board. Conduct pre- and post-layout power integrity, signal integrity, and IR/droop simulations using industry-standard 2.5D/3D field solvers and circuit simulators. Lead post-silicon validation and silicon power integrity measurements to correlate lab data with pre-silicon models, while collaborating with hardware teams to validate platforms under dynamic workloads. Automate power integrity analysis and simulation scripts using Python, Tcl, or SKILL.
Required Qualifications
- Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field
- Proven industry experience in Power Integrity (PI), Power Architecture for SoCs and advanced 2.5D/3D/MCM packaging
- Deep understanding of System-on-Chip (SoC) power distribution, package stack-ups, bump/ball maps, and silicon-package interactions
- Hands-on expertise with high-speed lab equipment (VNAs, oscilloscopes, active probes, impedance analyzers, loadsteppers) for physical power validation and PDN characterization
- Strong foundation in power architecture, electromagnetics, transmission line theory, s-parameters, and power distribution network (PDN) noise dynamics
- EM & Extraction: Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, or Keysight ADS
- Circuit & PDN Simulation: HSPICE, Spectre, ADS, or SIMPLIS/SIMetrix
Desired Qualifications
- Automation & Scripting: Proficiency in Python, Tcl, Perl, or Cadence SKILL for automating simulation and extraction pipelines
- Behavioral Modeling: Experience with Verilog-A, AMS, or SystemC for macro-level system power modeling
- Interface Noise Co-Design: Familiarity with high-speed interfaces (e.g., PCIe, DDR, UCIe, die-to-die interconnects) and mitigating power supply switching noise impacts on high-speed signals
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.